The present invention relates generally to memory integrated circuits. More particularly, the present invention relates to accurate sensing of data in page mode memory integrated circuits which sense a large number of bits simultaneously.
A memory integrated circuit includes a plurality of core cells arranged in an array. Each core cell is uniquely addressable for writing and reading data. In a non-volatile memory such as a flash or electrically eraseable programmable read only memory (EEPROM), each core cell includes a control gate coupled to a word line for read/write access to a bit line and a transistor having a floating gate for storing charge. The core cell is written and read by applying appropriate voltages to the bit line and the word line.
In a page mode memory, a plurality of multiple bit words of data are sensed in the memory substantially simultaneously. Subsequently, individual words of the plurality of words are presented at the output of the memory. In one example, a page of four words is initially read. Each word is sixteen bits wide and is subsequently available for reading.
The advantage of page mode operation is reduction of the access time necessary to read words on the page after the initial page access. The initial read operation requires the full random access read time, which is for example 80 ns. Subsequent reads from the same page require only a page access read time, which may be only 25 ns.
In page mode, at the time of the initial read operation, four 16 bit words, or a total of 64 bits, are sensed. Sensing is detecting the stored data state in the memory. This is done by detecting the current sunk by the selected core cell and comparing this read current with a reference current in a reference core cell.
In a nonvolatile memory such as a flash memory, a core cell is programmed by selectively storing charge on a floating gate. If charge is stored on the floating gate, the threshold voltage of the core cell transistor is high so that the transistor of the core cell is turned off when a word line voltage is applied to the control gate of the transistor. In the off state, the current sunk by the memory cell is only a few nanoamps. If no charge is stored on the floating gate, the threshold voltage of the core cell transistor is low enough so that the transistor is turned on when a word line voltage is applied on the control gate of the core cell. When the transistor of the core cell is turned on, the core cell will sink approximately 10 to 20 .mu.A. In page mode, this current can vary from essentially 0 amps to 64.times.20 .mu.A=1.28 mA.
The read current flows in the core cells from bit lines connecting each column of the core cell array to ground. Ground potential is typically provided in the core cell array on a diffused semiconductor layer doped n+ to minimize its sheet resistance. Also, these ground paths may be intermittently strapped to Vss using a high conductivity layer such as metal. However, the read current in the diffused ground paths causes the ground node in the core cell array to vary from true ground. This establishes a source bias, in which the source of the core cell transistor is a few hundred microvolts or a few millivolts above ground potential, or Vss. In the same transistor, the bulk or body potential is quite close to Vss. This can cause a body effect in the core cell transistor in which the threshold voltage varies and the read current is reduced. Read current in a core cell may be only 6 or 7 .mu.A.
Moreover, the read current in the array and therefore the source bias in the individual core cells varies as a function of the stored data states of the core cells. If charge is not stored in the floating gates of many or most core cells, the read current will be higher than otherwise. Still further, the read current in the array and the source bias in the core cells varies with the selected location in the array and with the data stored in the vicinity of the selected location.
The effect of this current in the ground bus of the core cell array current and source bias in the core cells is to change the sense margin of the circuit which senses the read current in the selected core cell. As noted, the sensing circuit operates by comparing the selected cell's read current, which may be approximately 0 to 10 microamps, with a reference current having a value of, for example, 5 .mu.A. If, due to current in the ground bus, the read current in the core cells varies only between approximately 0 .mu.A and 6 or 7 .mu.A, the reference current is no longer centered in the read current range. This will skew the read access times. Moreover, because of the great variability of the read current, the read access times for the core cells will vary randomly and unpredictably across the core cell array. The operation of the memory will be slowed and accurate read data may not result.
The problem is enhanced with a new design involving page mode reading of 16 bit words. Previously, in a memory in which only a single 16 bit word was read, the total ground current was only 16.times.20 .mu.A or 320 .mu.A. In a page mode device, as noted, four or more words are simultaneously sensed so that the current in the ground bus may be at least four times as great. As noted, though, this current is completely unpredictable in its location and magnitude.
Accordingly there is a need for an improved memory and method for sensing data in a page mode memory which can rapidly and reliably sense the data states in the selected core cells without error or delay due to the current in the core cell array.